1. Field
Example embodiments disclosed herein relate to a semiconductor memory device, and more particularly, to a phase change memory device and related methods.
2. Description of Related Art
Demands for semiconductor memory devices have increased because of their advantages. For example, some of the advantages of semiconductor memory devices are random accessibility and higher integration and capacity storage than other memory devices. A flash memory device as a semiconductor memory device is commonly used in various portable electronic devices. Besides that, a semiconductor memory device substituting a capacitor of a dynamic random access memory (DRAM) for a non-volatile material has been used conventionally. Examples are a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive layer (TMR), and a phase change memory device using chalcogenide alloys. A multi-level phase change memory device is a non-volatile memory device whose manufacturing processes are relatively simple such that low-cost high capacity memory can be achieved.
A phase change memory cell generally utilizes diverse materials that can electrically change between various structured states. The various structured states respectively represent different electrical read-out characteristics. For example, there are memory devices formed of a chalcogenide material (hereinafter, referred to as a GST material), i.e., a germanium(Ge)-stibium(Sb)-tellurium(Te) compound. The GST material may be programmed into a state between an amorphous state generally having a relatively high resistivity and a crystalline state generally having a relatively low resistivity. The phase change memory cell may be programmed through the heating of the GST material. The time duration and temperature of the heating may determine whether the GST material remains in an amorphous state or a crystalline state. High resistivity and low resistivity may represent programmed values 0 and 1, respectively, which may be sensed by measuring a resistance of the GST material.
In a typical phase change memory device, a memory cell includes a resistance device and a switching device. FIGS. 1A and 1B are circuit diagrams representing a memory cell of a phase change memory device. Referring to FIG. 1A, a memory cell 10 of the phase change memory device includes a resistance device (i.e., a variable resistor 11 and a switching device (i.e., an access transistor 12).
As shown in FIG. 1A, a variable resistor 11 is connected to a bit line BL, and the access transistor 12 is connected between the variable resistor 11 and a ground. A word line WL is connected to a gate of the access transistor 12. Once a desired and/or predetermined voltage is applied to the word line WL, the access transistor 12 is turned on. Once the access transistor 12 is turned on, the variable resistor 11 receives current through the bit line BL.
FIG. 1B is a circuit diagram of a memory cell 20. The memory cell 20 includes a variable resistor 21 as the resistance device and a diode 22 as the switching device. The diode 22 is turned on or off depending on a word line voltage.
The variable resistors 11 and 21 may include a phase change material (not shown). The phase change material may have one of two stable states (e.g., a crystal state and an amorphous state). The phase change material changes into a crystal state or an amorphous state according to current supplied through a bit line BL. Programming data of a phase change memory device takes advantage of the above characteristic of the phase change material. The switching device can be realized with various devices such as a MOS transistor and a diode.
FIG. 2 is a graph illustrating characteristics of a phase change material, which may be used as a variable resistor. The curve (1) of FIG. 2 indicates a temperature condition that allows a phase change material to change into an amorphous state. The curve (2) of FIG. 2 indicates a temperature condition that allows a phase change material to change into a crystal state. Referring to the curve (1), the phase change material becomes an amorphous state after heating the phase change material at a temperature higher than a melting temperature Tm through supply of a current pulse until time T1 and then rapidly quenching the temperature of the phase change material. The amorphous state may be referred to as a reset state and may correspond to data 1. Referring to the curve (2), the phase change material becomes a crystal state after heating the phase change material for a longer time T2 than the time T1 at a temperature higher than a crystallization temperature Tc but lower than the melting temperature Tm and then quenching the temperature of the phase change material as a rate slower than used to quench the temperature of the phase change material to set the material in the amorphous state. The crystal state may be referred to as a set state and may correspond to data 0. The resistance of a memory cell varies depending on an amorphous volume. Typically, the memory cell's resistance is the highest when the phase change material is in an amorphous state and is the lowest when the phase change material is in a crystal state.
Recently, a technique storing more than 2-bit data in one memory cell is under development. This type of memory cell is generally referred to as a multi-level cell (MLC). In a phase change memory device, the MLC has intermediate states between a reset state and a set state.